Schematic Design Of Transistor Level NAND & NOR Gate
NAND Circuit
Components Required -
- 2 PMOS
- 2 NMOS
- 1 VDD
- 1 GND
Circuit Connections -
- Drag the PMOS, NMOS, VDD and GND components to the workspace
- Connect the upper node of both the PMOS to VDD
- Middle nodes of PMOS 1 and NMOS 1 are connected to input 1 and middle nodes of PMOS 2 and NMOS 2 are connected to input 2 respectively
- Lower node of NMOS 2 is connected to GND and lower node of NMOS 1 is connected to the upper node of NMOS 2.
- Upper node of NMOS 1 is connected to the output 1
- Lower node of both the PMOS are connected to the output
Observations -
- On clicking "validate" option after completing the circuit (assuming all connections are done correctly) you should see a table on the right side of the workspace
- By default, both the inputs have been set to 1 and the corresponding output observed is 0. To check otherwise, double-click the input.
Psuedo NMOS
Components Required -
- 2 PMOS
- 2 NMOS
- 1 VDD
- 1 GND
Circuit Connections -
- Drag the PMOS, NMOS, VDD and GND components to the workspace
- Connect the upper node of PMOS 1 to VDD
- Middle nodes of PMOS 1 and NMOS 1 are connected to input 1 and middle nodes of PMOS 2 and NMOS 2 are connected to input 2 respectively
- Lower node of PMOS 2 is connected to Output and lower node of PMOS 1 is connected to the upper node of PMOS 2.
- Upper nodes of NMOS 1, NMOS 2 are connected to the output 1
- Connect the lower nodes of NMOS 1 and NMOS 2 to Ground.
Observations -
- On clicking "validate" option after completing the circuit (assuming all connections are done correctly) you should see a table on the right side of the workspace
- By default, both the inputs have been set to 1 and the corresponding output observed is 0. To check otherwise, double-click the input.