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Aim

Theory

Objective

Procedure

Pretest

Demo

Practice

Assignment

Posttest

References

Contributors

Feedback

Schematic Design Of Transistor Level NAND & NOR Gate

Choose difficulty:

Beginner

Intermediate

Advanced

1. Which of the following gates gives 1 as the output only when its inputs are 0 only?

a: NAND Explanation

Explanation

b: XOR Explanation

Explanation

c: XNOR Explanation

Explanation

d: NOR Explanation

Explanation

2. Which of the following logic gates are functionally complete?

a: OR Explanation

Explanation

b: XOR Explanation

Explanation

c: NAND Explanation

Explanation

d: AND Explanation

Explanation

3. An inverter can be realized as?

a: i, iii Explanation

Explanation

b: ii, iv Explanation

Explanation

c: All Explanation

Explanation

d: iii, iv Explanation

Explanation

4. In CMOS NAND gate the NMOS are in

a: Series Explanation

Explanation

b: Parallel Explanation

Explanation

c: Random Explanation

Explanation

d: Series or Parallel Explanation

Explanation

5. Which of the following are universal gates?

a: NAND Explanation

Explanation

b: NOR Explanation

Explanation

c: OR Explanation

Explanation

d: Both a and b Explanation

Explanation

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