SR Latch (NOR-based)

Figure 1: NOR-based SR Latch circuit diagram showing cross-coupled NOR gates with S (Set) and R (Reset) inputs. Reference: Basic latch implementation

An SR latch is a basic memory element that can store one bit of information. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q, while Q' represents the complement of Q. This latch has two control inputs: S (Set) and R (Reset).

Operation Principle

• Hold State: When both S and R inputs are low (0), the latch maintains its current state through cross-coupled feedback
• Set State: When S is high (1) and R is low (0), the output Q is forced to high (1)
• Reset State: When R is high (1) and S is low (0), the output Q is forced to low (0)
• Invalid State: When both S and R are high (1), both outputs become low, violating the complementary relationship

Logic Equations

For NOR-based SR Latch (see the figure: R and Q' feed the gate whose output is Q, S and Q feed the gate whose output is Q'):

$$Q = \overline{R + Q'}$$

$$Q' = \overline{S + Q}$$

Where:

• $Q$ is the current output state
• $Q'$ is the complement of $Q$
• $S$ is the Set input
• $R$ is the Reset input

When S = R = 1, both equations give 0, so Q = Q' = 0, which is the invalid state of the table below.

Truth Table

S	R	Q	Q'	State
0	0	Q	Q'	Hold (No Change)
1	0	1	0	Set
0	1	0	1	Reset
1	1	0	0	Invalid

Key Features

• Basic bistable memory element
• Asynchronous operation (no clock required)
• Two stable states for storing binary information
• Forms the foundation for more complex memory circuits
• Invalid state occurs when both inputs are active

Applications

• Basic memory storage in digital circuits
• Foundation for building flip-flops
• Control circuits and state machines
• Temporary data storage in processors

SR Latch (NAND-based)

Figure 2: NAND-based SR Latch circuit diagram showing cross-coupled NAND gates with active-low S' and R' inputs. Reference: Alternative latch implementation

This is an alternate implementation of the SR latch built with NAND logic gates. Set and reset now become active low signals, denoted S' and R' respectively. The operation is identical to the NOR-based SR latch, but with inverted control signals.

Operation Principle

• Hold State: When both S' and R' inputs are high (1), the latch maintains its current state
• Set State: When S' is low (0) and R' is high (1), the output Q is forced to high (1)
• Reset State: When R' is low (0) and S' is high (1), the output Q is forced to low (0)
• Invalid State: When both S' and R' are low (0), both outputs become high, creating an invalid condition

Truth Table

S'	R'	Q	Q'	State
1	1	Q	Q'	Hold (No Change)
0	1	1	0	Set
1	0	0	1	Reset
0	0	1	1	Invalid

Logic Equations

For NAND-based SR Latch:

$$Q = \overline{S' \cdot Q'}$$

$$Q' = \overline{R' \cdot Q}$$

Where:

• $S'$ is the active-low Set input
• $R'$ is the active-low Reset input
• The operation is equivalent to NOR-based latch with inverted inputs

Key Features

• Active low control signals
• Equivalent functionality to NOR-based SR latch
• Historically more prevalent in digital systems
• NAND gates are often easier to implement in integrated circuits

Gated SR Latch

Figure 3: Gated SR Latch circuit diagram showing the addition of enable input for controlled operation. Reference: Circuit implementation

The Gated SR Latch is an enhancement of the basic SR latch that includes an enable (EN) or clock (CLK) input. This addition provides better control over when the latch can change state, making it more suitable for synchronous digital systems.

Operation Principle

• Disabled State: When EN = 0, the latch is disabled and maintains its current state regardless of S and R inputs
• Enabled State: When EN = 1, the latch operates like a normal SR latch based on S and R inputs
• Transparent Mode: While enabled, changes in S and R inputs immediately affect the output

Truth Table

EN	S	R	Q	Q'	State
0	X	X	Q	Q'	Hold (Disabled)
1	0	0	Q	Q'	Hold (No Change)
1	1	0	1	0	Set
1	0	1	0	1	Reset
1	1	1	X	X	Invalid

Logic Equations

For Gated SR Latch:

$$Q = S \cdot EN + Q \cdot \overline{(R \cdot EN)}$$

$$Q' = R \cdot EN + Q' \cdot \overline{(S \cdot EN)}$$

Where:

• $EN$ is the Enable/Clock input
• $S$ is the Set input
• $R$ is the Reset input
• When $EN = 0$, the latch holds its previous state
• When $EN = 1$, it behaves like a normal SR latch

Key Features

• Controlled operation through enable input
• Bridge between asynchronous latches and synchronous flip-flops
• Level-triggered operation (transparent when enabled)
• Foundation for edge-triggered flip-flops
• Eliminates unwanted state changes when disabled

Applications

• Building block for flip-flops
• Temporary data storage with controlled access
• Interface between asynchronous and synchronous circuits
• Memory elements in simple digital systems

JK Flip-Flop

Figure 4: Symbol of a JK Flip-Flop. The small circle at the clock input means that the flip-flop is triggered by the falling (negative) edge of the clock. The internal structure is shown in Figure 5. Reference: Circuit implementation

The JK flip-flop is an improved version of the SR flip-flop that eliminates the invalid state problem. It has two data inputs J and K, along with a clock input for synchronous operation. The JK flip-flop can perform all four basic operations: hold, set, reset, and toggle.

Operation Principle

• Hold: When J = 0 and K = 0, the output remains unchanged
• Set: When J = 1 and K = 0, the output Q becomes 1
• Reset: When J = 0 and K = 1, the output Q becomes 0
• Toggle: When J = 1 and K = 1, the output toggles to its complement

Truth Table

J	K	CLK	Q(n+1)	Operation
0	0	↓	Q(n)	Hold
1	0	↓	1	Set
0	1	↓	0	Reset
1	1	↓	Q'(n)	Toggle

↓ is the active (falling) edge of the clock, as in the symbol of Figure 4. The same flip-flop with a rising-edge trigger would use ↑.

Characteristic Equation

$$Q(n+1) = J \cdot \overline{Q(n)} + \overline{K} \cdot Q(n)$$

Key Features

• Eliminates the invalid state of SR flip-flop
• Edge-triggered operation for synchronous circuits
• Toggle capability makes it versatile for counters
• Can implement any other type of flip-flop
• Most versatile flip-flop design

Applications

• Binary counters and frequency dividers
• State machines and sequential logic
• Memory registers in processors
• Control circuits in digital systems

Master-Slave JK Flip-Flop

Figure 5: Master-Slave JK Flip-Flop circuit diagram showing the two-stage latch configuration to eliminate race conditions. Reference: Advanced flip-flop implementation

The Master-Slave JK flip-flop consists of two SR latches connected in series to prevent race-around conditions. The master latch is enabled during the positive half of the clock cycle, while the slave latch is enabled during the negative half.

Operation Principle

Positive Clock Edge:

• Master latch accepts J and K inputs
• Slave latch is disabled, maintaining previous output
• M and M' are the outputs of the master latch, and they follow J and K (and the fed-back outputs Q and Q') while the clock is high

Negative Clock Edge:

• Master latch is disabled, holding its state
• Slave latch transfers the master's state to the output

Internal Signal Relationships

In the master-slave configuration shown:

• M, M': Outputs of the master latch, passed to the slave latch
• Master inputs: the master latch is set when J = 1, CLK = 1 and Q' = 1, and it is reset when K = 1, CLK = 1 and Q = 1
• Slave latch: copies M and M' to Q and Q' while the clock is low (the clock input of the slave is the inverted clock)
• NAND implementation (as in the Demo and in Practice task 3): the master latch is driven by the active-low signals $S' = \overline{J \cdot CLK \cdot \overline{Q}}$ and $R' = \overline{K \cdot CLK \cdot Q}$

Because Q and Q' are fed back to the master only, they cannot change while the clock is high. This is why J = K = 1 toggles the output once per clock pulse, and not repeatedly, as it does in a single JK latch.

JK Timing Diagram

Figure 5a: JK Flip-Flop timing diagram showing the relationship between clock, inputs (J, K), and output (Q) over time. Reference: Timing analysis

The timing diagram shows how the JK flip-flop output changes with respect to the clock and input signals. Key observations:

• Output changes occur on the falling edge of the clock (negative edge triggered)
• J and K inputs are sampled during the positive clock period
• Output is stable during the positive clock period
• Race-around condition is eliminated by the master-slave configuration

Key Features

• Eliminates race-around problems in JK flip-flops
• Edge-triggered operation with well-defined timing
• Internal isolation between input sampling and output changes
• Robust operation in high-speed digital systems

D Flip-Flop

Figure 6: D Flip-Flop circuit diagram showing the simple data transfer mechanism with clock synchronization. Reference: Circuit implementation

A D flip-flop, also known as a "data flip-flop" or "delay flip-flop," is used to store a single bit of data. It has only one data input (D) along with a clock input, making it simpler than the JK flip-flop while eliminating timing issues.

Operation Principle

The D flip-flop transfers the data input to the output on each clock edge. The operation is straightforward:

• When the clock triggers, Q becomes equal to D
• The output remains stable until the next clock edge
• There are no invalid states or race conditions

Truth Table

D	CLK	Q(n+1)	Operation
0	↓	0	Store 0
1	↓	1	Store 1
X	No Edge	Q(n)	Hold

The D flip-flop of the figure is an SR flip-flop with D connected to S and the complement of D connected to R, so that S and R can never be 1 together. In Practice task 2 the RS flip-flop block responds while its clock input is 1, so Q follows D during the clock pulse.

Characteristic Equation

$$Q(n+1) = D$$

Key Features

• Single data input eliminates invalid states
• Simple and reliable operation
• Edge-triggered for synchronous systems
• Excellent for data storage and transfer
• No race conditions or timing issues

Applications

• Data registers and memory units
• Shift registers for serial data processing
• Pipeline stages in processors
• Synchronization of asynchronous signals
• Temporary storage in digital systems

T Flip-Flop

Figure 7: T Flip-Flop circuit diagram showing the toggle mechanism implementation. Reference: Circuit implementation

A T flip-flop, or Toggle flip-flop, changes its output state on each clock pulse when the T input is high. It is particularly useful for frequency division and counter applications.

Operation Principle

• Hold: When T = 0, the output remains unchanged regardless of clock edges
• Toggle: When T = 1, the output toggles (changes to its complement) on each clock edge

Truth Table

T	CLK	Q(n+1)	Operation
0	↓	Q(n)	Hold
1	↓	Q'(n)	Toggle

Characteristic Equation

$$Q(n+1) = T \oplus Q(n)$$

Key Features

• Simplest flip-flop for toggle operations
• Divides input frequency by 2 when T = 1
• Can be constructed from JK flip-flop (J = K = T)
• Edge-triggered operation
• Essential building block for counters

Applications

• Binary counters and frequency dividers
• Clock generation circuits
• Ripple counters in digital systems
• Pulse shaping and timing circuits
• State toggles in control systems

Conversion from JK Flip-Flop

A T flip-flop can be easily implemented using a JK flip-flop by connecting both J and K inputs together to form the T input:

$$T = J = K$$

This configuration ensures that when $T = 1$, both $J = K = 1$, causing the toggle operation.

Timing Considerations

• Setup Time: T input must be stable before clock edge
• Hold Time: T input must remain stable after clock edge
• Propagation Delay: Time between clock edge and output change
• Maximum Frequency: Limited by internal gate delays

Implementation Variations

1. Using JK Flip-Flop: Connect J and K inputs together
2. Using D Flip-Flop: Connect output $Q$ back to the D input through an XOR gate with T, so that $D = T \oplus Q$ (when T = 1, D = Q' and the output toggles)
3. Direct Implementation: Custom logic gates for toggle function

Comparison of Flip-Flop Types

Type	Inputs	Key Feature	Primary Use
SR	S, R, CLK	Basic set/reset	Foundation circuits
JK	J, K, CLK	Eliminates invalid state	Universal flip-flop
D	D, CLK	Single data input	Data storage
T	T, CLK	Toggle operation	Counters, frequency division

Practical Design Considerations

Timing Parameters

• Setup Time ($t_{su}$): Minimum time data must be stable before clock edge
• Hold Time ($t_h$): Minimum time data must be stable after clock edge
• Propagation Delay ($t_{pd}$): Time from clock edge to output change
• Clock-to-Output Delay: Specific propagation delay measurement

Power Consumption

• Static Power: Power consumed when flip-flop is not switching
• Dynamic Power: Power consumed during state transitions
• Clock Power: Power consumed by clock distribution network

Metastability

When setup/hold times are violated, flip-flops may enter metastable states:

• Cause: Insufficient setup or hold time
• Effect: Unpredictable output for extended period
• Mitigation: Proper timing analysis and synchronizer circuits

Notes on the Simulation

• Every task starts in the SET state, Q = 1 and Q' = 0.
• In Practice tasks 1, 2 and 4 the circuit (a gated SR latch, and the RS and JK flip-flop blocks) changes its output while its clock input is 1 and holds its value while the clock is 0.
• Task 3 asks for a master-slave JK flip-flop, which changes its output only when the clock falls. The check of this task therefore applies a complete clock pulse (the clock goes to 1 and then to 0) for every combination of J and K.
• A single gated JK latch, without the master-slave arrangement, does not pass task 3: with J = K = 1 and the clock high, its output keeps changing (the race-around condition).