The objective of this experiment is to design and analyze different types of latches and flip-flops. You will be able to build an RS, D, JK and T flip-flop, and understand how a clock and the master-slave configuration control when the stored bit changes.

• RS Flip-Flop: Build a clocked set-reset flip-flop (a gated SR latch) from NAND gates, or from AND and NOR gates
• D Flip-Flop: Build a data flip-flop from an RS flip-flop, so that Q follows D when the clock is applied
• JK Flip-Flop: Construct a versatile flip-flop that eliminates the forbidden state, in the master-slave configuration
• T Flip-Flop: Create a toggle flip-flop from a JK flip-flop for frequency division applications
• Master-Slave Configuration: Understand dual-stage flip-flop design for race-free operation

Through this experiment, students will gain practical experience in sequential circuit design and understand the fundamental principles of memory elements and timing control in digital systems.