Virtual Labs

1. If S=0, R=1, CLK=X (don't care), then what is the output of an SR flip-flop:

a: No change Explanation

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b: SET Explanation

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c: RESET Explanation

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d: TOGGLE Explanation

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2. In a D flip-flop, when the clock transitions from low to high and D=1, what happens to the output Q:

a: Q remains unchanged Explanation

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b: Q becomes 0 Explanation

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c: Q becomes 1 Explanation

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d: Q toggles Explanation

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3. What input is required to make a JK flip-flop toggle its output:

a: J=1 and K=0 Explanation

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b: J=0 and K=0 Explanation

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c: J=0 and K=1 Explanation

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d: J=1 and K=1 Explanation

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4. Which of the following is a key advantage of Master-Slave flip-flops over simple latches:

a: Lower power consumption Explanation

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b: Elimination of race-around conditions Explanation

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c: Faster operation Explanation

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d: Simpler circuit design Explanation

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5. In a T flip-flop, if T=1 and the initial state Q=0, what will be the output after two clock pulses:

a: Q=0 Explanation

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b: Q=1 Explanation

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c: Q=X (unknown) Explanation

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d: Q oscillates Explanation

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6. Which characteristic equation correctly represents a JK flip-flop:

a: Q(n+1) = J ⊕ K Explanation

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b: Q(n+1) = J · Q'(n) + K' · Q(n) Explanation

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c: Q(n+1) = J + K Explanation

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d: Q(n+1) = J · K · Q(n) Explanation

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7. In a gated SR latch, what happens when the enable signal (EN) is low:

a: The latch toggles continuously Explanation

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b: The latch follows S and R inputs Explanation

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c: The latch maintains its current state Explanation

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d: The latch resets to 0 Explanation

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8. What is the setup time requirement in flip-flop operation:

a: Time after clock edge when data must remain stable Explanation

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b: Time before clock edge when data must be stable Explanation

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c: Time between clock pulses Explanation

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d: Time for output to change after clock edge Explanation

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Latch and Flip-Flops