Tools

Detection of both SA0 and SA1 faults on a VLSI circuit for 3-bit EVEN parity generator circuit

References

  1. Digital Design with an Introduction to Verilog", Morris Mano, Pearson Education India, 5th Edition, 2013.
  2. Digital Logic Design", B. Holdsworth and R.C. Woods, 4th Edition, Elsevier, 2003.
  3. Digital System Test and Testable Design, by Zainalabedin Navabi.