Detection of both SA0 and SA1 faults on a VLSI circuit for 3-bit EVEN parity generator circuit
Aim
To analyze and detect stuck-at faults and to determine the output of the 3-bit even parity generator by using 2-input Ex-OR gates
To analyze and detect stuck-at faults and to determine the output of the 3-bit even parity generator by using 2-input Ex-OR gates