Detection of both SA0 and SA1 faults on a VLSI circuit for 3-bit EVEN parity generator circuit
Lab Developers:
| SNo. | Name | Institute |
|---|---|---|
| 1 | Dr. Biswajit R Bhowmik | NITK |
| 2 | Prof. K V Gangadharan | NITK |
Contributors :
| SNo. | Name | Institute |
|---|---|---|
| 1 | Akshaya | NITK |
| 2 | Vismaya M Kumar | NITK |
| 3 | Anusha B Salian | NITK |