Design of Register using Verilog
In the Verilog implementation of a SISO register, what is the purpose of the non-blocking assignment (<=)?
What is the delay between input and output in a 4-bit SISO register?
What happens to the data in a SISO register when the reset signal is active?
Which Verilog construct is used to implement the sequential behavior of a register?
What is the main advantage of using a SISO register over a parallel register?