The aim of this experiment is to design and simulate a 4-bit Serial In Serial Out (SISO) register using Verilog HDL. Through this experiment, students will:

1. Understand the concept of sequential circuits and registers
2. Learn how to implement a SISO register using Verilog
3. Study the behavior of shift registers through simulation
4. Analyze the timing characteristics of sequential circuits
5. Gain hands-on experience with Verilog coding for sequential logic