Design a 2-bit multiplier circuit as given in the theory section. The circuit should take 2 inputs (A₁A₀ and B₁B₀) and produce a 4-bit output (P₃P₂P₁P₀). Use AND gates for partial product generation and half/full adders for summation.

Construct a 4-bit binary multiplier using array multiplier architecture. Given two 4-bit binary numbers A₃A₂A₁A₀ and B₃B₂B₁B₀, the circuit should output an 8-bit product P₇P₆P₅P₄P₃P₂P₁P₀. For circuit diagram, refer to the theory section.

Design a 3-bit Wallace tree multiplier using AND gates, half adders, and full adders. Given A₂A₁A₀ and B₂B₁B₀, the circuit should output P₅P₄P₃P₂P₁P₀. Analyze the delay reduction compared to array multiplier and explain the compression stages.

Can a 2-bit multiplier be implemented using only NAND gates? If yes, design the circuit and explain the implementation. If no, explain why other gates are necessary for efficient multiplication.