Extraction of MOSFET LEVEL (1,2,3 and 6) SPICE parameters related to gate voltage Capacitance (Cg vs. Vg) 
1. What two quantities are typically plotted against each other to characterize a MOSFET's gate capacitance?
2. The maximum capacitance value, measured in the 'accumulation' region, is directly used to calculate which physical SPICE parameter?
3. The *minimum* capacitance value, observed just before strong inversion, is primarily used to extract which SPICE parameter?
4. In the 'accumulation' region of an NMOS C-V plot (at negative gate voltage), the measured capacitance is high because...
5. Why does the measured gate capacitance *decrease* as the gate voltage sweeps from accumulation into the 'depletion' region?
6. In a *high-frequency* C-V measurement, why does the capacitance remain *low* in the 'inversion' region (unlike a low-frequency measurement)?
7. What is the primary visual effect of a high density of interface traps (e.g., `NFS` in LEVEL 3) on the C-V curve's shape?
8. Which SPICE parameter represents the gate voltage where there is no electric field in the silicon, typically extracted from the start of the 'depletion' slope?
9. In advanced models (LEVEL 6/BSIM), what physical effect in the *gate material itself* causes a slight *drop* in capacitance when the device is strongly inverted?
10. Quantum mechanical (QM) effects, modeled in LEVEL 6, cause the charge in the inversion layer to be pushed slightly away from the oxide, resulting in...