Virtual Labs

Dynamic Scheduling with Tomasulo Algorithm

After using the simulator, what did you observe about the register alias table when multiple instructions write to the same register?

a: The system generates an error message Explanation

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b: Only the first instruction proceeds Explanation

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c: Each instruction gets assigned a different reservation station tag Explanation

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d: All instructions stall until resolved Explanation

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Based on your simulation experience, what happens when an instruction's operands become available?

a: The instruction immediately completes execution Explanation

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b: The instruction becomes ready and can begin execution when a functional unit is free Explanation

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c: The instruction is removed from the reservation station Explanation

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d: The instruction broadcasts its result on the CDB Explanation

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In the simulation, what visual indicator shows that an instruction is waiting for operands?

a: The instruction appears in red color Explanation

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b: Reservation station tags appear in the Qj/Qk fields instead of values Explanation

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c: The instruction shows 'BLOCKED' status Explanation

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d: The functional unit indicator blinks Explanation

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From your simulation experience, what did you observe about instruction completion order?

a: Instructions always complete in program order Explanation

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b: Instructions complete in reverse program order Explanation

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c: Instructions complete out-of-order based on operand availability and execution time Explanation

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d: Instruction completion order is random Explanation

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What performance metric did you notice improved most with the Tomasulo algorithm?

a: Individual instruction execution time Explanation

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b: Memory access latency Explanation

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c: Overall instruction throughput (IPC - Instructions Per Cycle) Explanation

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d: Cache hit rate Explanation

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During simulation, when did you observe the Common Data Bus (CDB) being most active?

a: When instructions are being issued to reservation stations Explanation

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b: When multiple instructions complete execution simultaneously Explanation

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c: When the processor is idle Explanation

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d: When instructions are waiting for operands Explanation

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What did you observe about reservation station utilization during long dependency chains?

a: Reservation stations remain mostly empty Explanation

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b: Only one type of reservation station is used Explanation

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c: Reservation stations fill up with waiting instructions Explanation

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d: Reservation stations are bypassed entirely Explanation

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After experimenting with the simulator, which factor most significantly limits instruction-level parallelism?

a: Number of reservation stations available Explanation

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b: True data dependencies (RAW hazards) between instructions Explanation

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c: Speed of the Common Data Bus Explanation

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d: Complexity of the register renaming hardware Explanation

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Based on your simulation analysis, what would be the most effective way to improve performance in a workload with frequent structural hazards?

a: Increase the number of reservation stations Explanation

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b: Reduce instruction execution latencies Explanation

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c: Improve branch prediction accuracy Explanation

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d: Increase memory bandwidth Explanation

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