Virtual Labs

Schematic Design Of Transistor Level Inverter

1. The number of inputs in an inverter is ____.

a: 1 Explanation

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b: 2 Explanation

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c: 3 Explanation

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d: 4 Explanation

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2. Inverter gate is same as __________.

a: AND gate Explanation

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b: NOT gate Explanation

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c: NOR gate Explanation

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d: NAND gate Explanation

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3. Which is the most suitable representation for a NOT gate?

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b: <

> Explanation

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4. Identify which statement is true for inverter?

a: Any difference in inputs guarantees a high output Explanation

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b: Any difference in inputs guarantees a low output Explanation

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c: A high input gives a high output Explanation

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d: A low input gives a high output Explanation

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5. What is the traditional symbol for inverter?

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6. Choose the electrical analogue of an inverter?

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d: None of these Explanation

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7. What is the correct input voltage range for region D?

a: V_dd/2 < V_in ≤ V_dd-V_tp Explanation

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b: V_in = V_dd/2 Explanation

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c: 0 ≤ V_in ≤ V_tn Explanation

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d: V_in ≥ V_dd-V_tp Explanation

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8. What are the operation states of n-device and p-device respectively in region B?

a: Linear & unsaturated Explanation

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b: Cut-off & linear Explanation

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c: Linear & saturated Explanation

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d: Saturated & linear Explanation

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9. What is delay?

a: Maximum of rise time and fall time Explanation

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b: Product of rise time and fall time Explanation

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c: Average of rise time and fall time Explanation

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d: Addition of rise time and fall time Explanation

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10. What is desirable β_n/β_p ratio for an inverter?

a: 0 Explanation

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b: 1 Explanation

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c: 0.5 Explanation

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d: ∞ Explanation

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