Virtual Labs

What type of data hazard occurs when an instruction needs a value that is yet to be written by a previous instruction?

a: WAR (Write After Read) Explanation

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b: WAW (Write After Write) Explanation

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c: RAW (Read After Write) Explanation

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d: No hazard Explanation

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Consider the following instruction sequence: 1. LOAD R1, 0(R2) 2. ADD R3, R1, R4 Which type of hazard may occur?

a: RAW hazard between instructions 1 and 2 Explanation

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b: WAW hazard between instructions 1 and 2 Explanation

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c: WAR hazard between instructions 1 and 2 Explanation

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d: No hazard Explanation

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What is the role of instruction scheduling in handling data hazards?

a: To add more hazards to test the pipeline Explanation

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b: To randomly shuffle instructions Explanation

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c: To reorder instructions to minimize stalls Explanation

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d: To ensure instructions always execute in the original order Explanation

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Given the sequence: 1. MUL R1, R2, R3 2. ADD R4, R1, R5 3. SUB R6, R4, R7 Which pairs of instructions have RAW hazards?

a: Only 1 → 2 Explanation

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b: Only 2 → 3 Explanation

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c: Both 1 → 2 and 2 → 3 Explanation

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d: No RAW hazards Explanation

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In a 5-stage pipeline without forwarding, what issue may arise in the following sequence? 1. MUL R1, R2, R3 2. DIV R4, R1, R5

a: R4 is written before R1 is read Explanation

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b: DIV may read stale value of R1 Explanation

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c: Both instructions are independent Explanation

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d: No hazard exists because they use different operations Explanation

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Which reordering of the following maintains correctness? Original: ADD R1, R2, R3; SUB R4, R1, R5; MUL R6, R4, R7

a: SUB; ADD; MUL Explanation

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b: ADD; MUL; SUB Explanation

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c: ADD; SUB; MUL Explanation

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d: MUL; SUB; ADD Explanation

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What hazard arises when instruction A writes to a register after instruction B reads it?

a: RAW Explanation

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b: WAR Explanation

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c: WAW Explanation

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d: No hazard Explanation

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Which of the following introduces a WAW hazard?

a: 1. ADD R1, R2, R3; 2. MUL R1, R4, R5 Explanation

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b: 1. LOAD R1, 0(R2); 2. ADD R3, R1, R4 Explanation

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c: 1. SUB R2, R3, R4; 2. DIV R1, R2, R5 Explanation

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d: 1. ADD R6, R7, R8; 2. STORE R6, 0(R1) Explanation

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What is a correct strategy to eliminate a WAR hazard in a pipeline?

a: Use forwarding Explanation

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b: Delay the read instruction Explanation

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c: Use register renaming Explanation

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d: Add more pipeline stages Explanation

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Data Hazards