Virtual Labs

In a pipelined processor, what kind of hazard occurs when a read instruction follows too closely after a write to the same register?

a: Structural hazard Explanation

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b: Control hazard Explanation

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c: Data hazard - RAW Explanation

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d: Data hazard - WAW Explanation

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Consider the following instruction sequence: 1. LOAD R1, 0(R2) 2. ADD R3, R1, R4 Which type of hazard may occur?

a: RAW hazard between instructions 1 and 2 Explanation

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b: WAW hazard between instructions 1 and 2 Explanation

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c: WAR hazard between instructions 1 and 2 Explanation

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d: No hazard Explanation

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Which of the following best describes a technique used to reduce data hazards during compile-time?

a: To add more hazards to test the pipeline Explanation

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b: To randomly shuffle instructions Explanation

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c: To reorder instructions to minimize stalls Explanation

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d: To ensure instructions always execute in the original order Explanation

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Identify the hazards in this reordered sequence: 1. ADD R1, R2, R3 2. SUB R4, R1, R5 3. MUL R1, R4, R6

a: Only 1 → 2 Explanation

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b: Only 2 → 3 Explanation

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c: Both 1 → 2 and 2 → 3 Explanation

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d: No RAW hazards Explanation

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How would a lack of load delay slots affect this instruction pair? 1. LOAD R1, 0(R2) 2. ADD R3, R1, R4

a: The ADD instruction may execute too early and use stale data. Explanation

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b: The ADD instruction will always execute correctly. Explanation

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c: There will be no performance penalty. Explanation

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d: The processor ignores hazards automatically. Explanation

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Choose the reordering that avoids data hazards without changing program behavior: Original: LOAD R1, 0(R2); ADD R3, R1, R4; STORE R3, 0(R5)

a: ADD; LOAD; STORE Explanation

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b: LOAD; STORE; ADD Explanation

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c: LOAD; ADD; STORE Explanation

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d: STORE; LOAD; ADD Explanation

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In the sequence: 1. LOAD R1, 0(R2) 2. STORE R1, 4(R3) 3. ADD R1, R1, R4 Which hazard could occur if instructions are issued without delay?

a: WAR hazard between 2 and 1 Explanation

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b: WAW hazard between 1 and 3 Explanation

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c: RAW hazard between 1 and 3 Explanation

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d: None, because R1 is not reused Explanation

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Which of the following introduces a WAW hazard?

a: 1. ADD R1, R2, R3; 2. MUL R1, R4, R5 Explanation

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b: 1. LOAD R1, 0(R2); 2. ADD R3, R1, R4 Explanation

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c: 1. SUB R2, R3, R4; 2. DIV R1, R2, R5 Explanation

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d: 1. ADD R6, R7, R8; 2. STORE R6, 0(R1) Explanation

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What is a correct strategy to eliminate a WAR hazard in a pipeline?

a: Use forwarding Explanation

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b: Delay the read instruction Explanation

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c: Use register renaming Explanation

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d: Add more pipeline stages Explanation

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Data Hazards