Data Hazards and Instruction Scheduling
In a pipelined processor, what kind of hazard occurs when a read instruction follows too closely after a write to the same register?
Consider the following instruction sequence:
1. LOAD R1, 0(R2)
2. ADD R3, R1, R4
Which type of hazard may occur?
1. LOAD R1, 0(R2)
2. ADD R3, R1, R4
Which type of hazard may occur?
Which of the following best describes a technique used to reduce data hazards during compile-time?
Identify the hazards in this reordered sequence:
1. ADD R1, R2, R3
2. SUB R4, R1, R5
3. MUL R1, R4, R6
1. ADD R1, R2, R3
2. SUB R4, R1, R5
3. MUL R1, R4, R6
How would a lack of load delay slots affect this instruction pair?
1. LOAD R1, 0(R2)
2. ADD R3, R1, R4
1. LOAD R1, 0(R2)
2. ADD R3, R1, R4
Choose the reordering that avoids data hazards without changing program behavior:
Original: LOAD R1, 0(R2); ADD R3, R1, R4; STORE R3, 0(R5)
Original: LOAD R1, 0(R2); ADD R3, R1, R4; STORE R3, 0(R5)
In the sequence:
1. LOAD R1, 0(R2)
2. STORE R1, 4(R3)
3. ADD R1, R1, R4
Which hazard could occur if instructions are issued without delay?
1. LOAD R1, 0(R2)
2. STORE R1, 4(R3)
3. ADD R1, R1, R4
Which hazard could occur if instructions are issued without delay?
Which of the following introduces a WAW hazard?
What is a correct strategy to eliminate a WAR hazard in a pipeline?