Virtual Labs

Directory-Based Cache Coherence Protocol Simulator

What is the primary purpose of directory-based cache coherence protocols?

a: To reduce cache size requirements Explanation

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b: To maintain coherence in large-scale multiprocessor systems without broadcast overhead Explanation

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c: To increase individual processor speed Explanation

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d: To simplify cache replacement algorithms Explanation

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In directory-based cache coherence, what information does a directory entry typically contain?

a: Only the current owner of the cache line Explanation

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b: Only the state of the memory block Explanation

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c: State, sharer vector, and owner information Explanation

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d: Only a list of processors that have accessed the block Explanation

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What are the three basic directory states in a typical directory-based protocol?

a: Read, Write, Execute Explanation

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b: Uncached, Shared, Exclusive Explanation

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c: Invalid, Valid, Modified Explanation

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d: Local, Remote, Distributed Explanation

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When a processor wants to read a block that is currently in the 'Exclusive' state in the directory, what happens?

a: The read request is denied Explanation

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b: The data is provided directly from memory Explanation

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c: A forward request is sent to the owner processor for cache-to-cache transfer Explanation

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d: All processors are invalidated first Explanation

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What is a major advantage of directory-based protocols over bus-based protocols like MSI?

a: Lower memory overhead Explanation

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b: Simpler implementation Explanation

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c: Better scalability with processor count Explanation

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d: Faster single-processor performance Explanation

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In a directory-based system, what happens when a processor wants to write to a block currently shared by multiple processors?

a: The write is performed immediately without any communication Explanation

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b: The directory sends invalidation messages to all current sharers before granting write access Explanation

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c: Only the requesting processor is invalidated Explanation

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d: The write is queued until all sharers voluntarily release the block Explanation

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What is the purpose of the sharer vector in a directory entry?

a: To track the order in which processors accessed the block Explanation

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b: To identify which processors currently have copies of the block in shared state Explanation

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c: To store the actual data values cached by each processor Explanation

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d: To record the performance statistics for each processor Explanation

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What is a potential bottleneck in directory-based cache coherence systems?

a: The directory itself becoming a hotspot for frequently accessed data Explanation

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b: Insufficient cache capacity in individual processors Explanation

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c: Limited instruction-level parallelism Explanation

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d: Inadequate branch prediction accuracy Explanation

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In large-scale systems, which directory organization strategy would be most suitable for minimizing directory access latency?

a: Centralized directory with all entries in one location Explanation

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b: Distributed directory with entries spread across memory controllers based on address mapping Explanation

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c: Replicated directory with identical copies at every processor Explanation

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d: Hierarchical directory with multiple levels of directory nodes Explanation

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