Virtual Labs

2. In a ripple carry adder, which of the following is not the correct representation of any of the intermediate outputs(output after every intermediate gate) or final outputs that are present at each stage of the adder:

a: A XOR B XOR Cin Explanation

Explanation

b: (A XOR B) AND Cin Explanation

Explanation

c: (A AND B) XOR Cin Explanation

Explanation

d: (A AND B) OR (Cin AND (A XOR B)) Explanation

Explanation

3. Which of the set of carry, sum values are not possible in a half adder circuit:

a: 0, 0 Explanation

Explanation

b: 1, 1 Explanation

Explanation

c: 0, 1 Explanation

Explanation

d: 1, 0 Explanation

Explanation

4. Half adder circuit is a combination of which of the following gates:

a: AND gate and XOR gate Explanation

Explanation

b: AND gate and OR gate Explanation

Explanation

c: XNOR gate and AND gate Explanation

Explanation

d: XNOR gate and NOT gate Explanation

Explanation

5. How many input lines are there in FULL ADDER circuit:

a: 1 Explanation

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b: 2 Explanation

Explanation

c: 3 Explanation

Explanation

d: 4 Explanation

Explanation

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