Schematic Design Of Transistor Level XOR & XNOR Gate
1. Which of the following gates can be used as even parity generator?
2. Reduce the expression xy(z+w)+y(xz+xz)+zw and tell the min number of transistor required for the design.
3. How many NOR gates are required for realizing XOR gate?
4. Which of the following gates can be used for parity detection?
5. What will be the minimum number of transistor required for designing xy+xz+zy+xy+z