Virtual Labs

Why is register renaming critical for modern superscalar pipelines?

a: It increases the clock frequency Explanation

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b: It simplifies compiler design Explanation

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c: It removes name-based hazards and improves parallelism Explanation

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d: It avoids instruction cache misses Explanation

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What type of hazards does register renaming specifically target?

a: RAW and structural Explanation

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b: Control and structural Explanation

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c: WAR and WAW Explanation

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d: Cache and branch hazards Explanation

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In the simulation, what does it mean if an architectural register maps to multiple physical registers across instructions?

a: The simulator has a bug Explanation

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b: This allows multiple writes to the same register without conflict Explanation

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c: This causes WAR hazards Explanation

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d: It prevents out-of-order execution Explanation

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What happens if there are no free physical registers during instruction issue?

a: The instruction is issued anyway Explanation

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b: A WAW hazard occurs Explanation

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c: The pipeline stalls until a physical register is freed Explanation

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d: The logical register is reused Explanation

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After an instruction writes its result, when can its physical register be reclaimed?

a: Immediately after execution Explanation

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b: After commit and once no other instructions depend on it Explanation

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c: After rename stage Explanation

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d: Never — physical registers are fixed Explanation

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What allows two instructions writing to the same architectural register to proceed out of order?

a: Delayed write-back Explanation

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b: Issuing instructions in-order Explanation

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c: Assigning a new physical register to the later instruction Explanation

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d: Skipping dependencies Explanation

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In a register rename table, what does a mapping like 'R5 → P8' indicate?

a: Register R5 is invalid Explanation

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b: P8 is the architectural register Explanation

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c: Physical register P8 holds the most recent value for R5 Explanation

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d: R5 has been renamed to R8 Explanation

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A student tries to write back a result, but the simulator blocks it. The rename table shows another instruction maps to the same architectural register. Why is this blocked?

a: A WAW hazard is pending and write-back is unsafe Explanation

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b: RAW hazard must be resolved first Explanation

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c: There are no more rename slots Explanation

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d: The functional unit is busy Explanation

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What would be the main limitation if register renaming is not used along with scoreboarding?

a: Only floating-point instructions can be executed Explanation

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b: Only one instruction can be in the pipeline at a time Explanation

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c: WAR and WAW hazards must be stalled instead of eliminated Explanation

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d: The rename table becomes too large Explanation

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