Virtual Labs

Reorder Buffer and Out-of-Order Execution

What is the primary purpose of a Reorder Buffer (ROB) in modern processors?

a: To increase cache hit rates Explanation

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b: To enable out-of-order execution while maintaining precise interrupts Explanation

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c: To reduce branch prediction penalties Explanation

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d: To improve memory bandwidth utilization Explanation

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In a processor with a Reorder Buffer, instructions are committed in which order?

a: The order they complete execution Explanation

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b: Based on their priority level Explanation

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c: In program order (sequential order) Explanation

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d: Random order to maximize throughput Explanation

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What information is typically stored in each Reorder Buffer entry?

a: Only the instruction opcode Explanation

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b: Instruction type, destination register, value, and completion status Explanation

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c: Cache line addresses and memory mappings Explanation

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d: Branch prediction history Explanation

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How does the Reorder Buffer help with register renaming?

a: By providing additional physical registers Explanation

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b: By serving as temporary names for destination registers Explanation

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c: By eliminating the need for registers entirely Explanation

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d: By reducing the number of required registers Explanation

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What happens when an exception occurs in an instruction within the Reorder Buffer?

a: The exception is handled immediately Explanation

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b: All instructions are flushed from the pipeline Explanation

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c: The exception is noted but handled only when the instruction reaches the head of ROB Explanation

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d: The instruction is retried automatically Explanation

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In the context of ROB, what does 'precise interrupt' mean?

a: Interrupts occur at exact time intervals Explanation

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b: The processor state appears as if instructions executed in program order Explanation

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c: Interrupts have higher priority than regular instructions Explanation

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d: The interrupt handler executes faster Explanation

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What is the main advantage of allowing out-of-order execution in processors?

a: Reduced power consumption Explanation

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b: Simplified processor design Explanation

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c: Better utilization of functional units and higher instruction throughput Explanation

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d: Smaller processor chip area Explanation

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Which type of dependency can be eliminated by register renaming in conjunction with ROB?

a: True data dependencies (RAW) Explanation

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b: Anti-dependencies (WAR) and output dependencies (WAW) Explanation

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c: Control dependencies Explanation

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d: Memory dependencies Explanation

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What determines the maximum number of instructions that can be 'in-flight' simultaneously in a processor with ROB?

a: The cache size Explanation

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b: The number of functional units Explanation

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c: The size of the Reorder Buffer Explanation

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d: The frequency of the processor Explanation

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