Experiment name
What is the main purpose of scoreboarding in a processor pipeline?
Which of the following hazards can scoreboarding handle?
In the scoreboarding algorithm, which stage waits for all operands to be ready?
Which of the following causes an instruction to stall at the Issue stage in scoreboarding?
What happens if a WAR hazard is detected during Write Result stage in a scoreboard-based pipeline?
If two instructions require the same functional unit type and one is executing, the second instruction:
Which instruction causes the first stall due to RAW hazard?
I1: MUL F0, F1, F2
I2: ADD F3, F0, F4
I3: SUB F5, F3, F6
In a scoreboarding simulation, what would prevent an instruction from writing its result?
Which of the following statements about scoreboarding is false?