Direct Mapped Cache Design
In k-way associative mapping, if k=1, then it becomes direct mapping
If memory has an access time of 100ns, access time of the cache memory is 40ns with 80% hit ratio, then what is the effective access time of the CPU?
Tag bits in direct mapping (assume, p is number of main memory blocks and q is number of cache blocks)
How many lines are there in a direct mapped cache having 23-bit tag and 1-word blocks?
Consider a memory system with cache and main memory. The cache is 5 times faster than the main memory, its hit ratio is 80%. If average access time is increased by 20% from 50ns, then will there be any change in hit ratio, if yes, how much?