Design Of Digital Circuits Using Verilog
1. Which is correct assignment for two input and gate shown in Fig.1? 
2. Which is correct assignment for tri state buffer shown in Fig.2 
3. Which is not a logical operator?
4. Which is/are bitwise operator(s) ? A) & B) ~ C) | D) ^
5. Which is not a correct statement? (A) >> is a shift right operator. (B) & is a reduction operator (C) === is a case equality operator (D) Y = (sel) ? A : B; is an example of conditional operator
6. Which is/are correct verilog code for Fig.3? 
7. Which is correct verilog code for Fig.4? 
8. Which is not a correct port assignment for a module? 
9. Which is/are not correct escaped characters? (A)\n for new line (B)\t for new tab (C) % for % (D)\for\ (E)\s for string
10. Which is/are showing incorrect result for given operands and operator ? (i) 1 > 0 -> 1 'b1 x 1 <= 0 -> x 10 < z -> x (ii) 4'b 1z0x == 4'b 1z0x -> x 4'b 1z0x != 4'b 1z0x -> x (iii) One multi-bit operand -> One single-bit result a = 4'b1001; c = |a; // c = 1|0|0|1 = 1 (iv) 4'b 1z0x === 4'b 1z0x -> 1 4'b 1z0x !== 4'b 1z0x -> 0