To understand and simulate the MSI (Modified-Shared-Invalid) cache coherence protocol used in multiprocessor systems. This experiment aims to:

1. Demonstrate Cache Coherence: Understand how the MSI protocol maintains data consistency across multiple processor caches in a shared memory multiprocessor system.

2. Visualize State Transitions: Observe how cache lines transition between Modified (M), Shared (S), and Invalid (I) states based on processor operations and bus activities.

3. Analyze Protocol Behavior: Study the interaction between processor requests (PrRd/PrWr), bus transactions (BusRd/BusRdX/BusUpgr), and cache state changes.