Schematic Design Of Transistor Level Inverter
To design and analyze the transistor-level schematic of a digital inverter using CMOS and Pseudo NMOS logic, and to study the effect of load capacitance and transistor dimensions on its performance.
To design and analyze the transistor-level schematic of a digital inverter using CMOS and Pseudo NMOS logic, and to study the effect of load capacitance and transistor dimensions on its performance.