Instructions
  • Please read the PROCEDURE section carefully before starting the simulation for the experiment.
  • The verilog module and testbench code are partially filled and divided into code blocks.
  • Drag and drop these code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks.
  • Once you have completed the code and rearranged the blocks as required, click on validate. This will give the output truth table as per the code and will also give a success/failure message accordingly.
  • Clicking on reset will reset the experiment and you can start your practice again.
Verilog Module

  • module

      (,

      (,

      (,

      ();

  •   always @(posedge

      or posedge ) begin

  •   if ()

         <= ;

  •   else <= ;

  •   end

  • endmodule

Testbench

  • module ;

  •   reg ,,;

  •   wire ;

  •    dut (

                        ,

                        ,

                        ,

                        );

  •   initial begin

        clk = 0; rst = 1; d = 0;

        #10 rst = 0;

        #10 d = 1;

        #10 d = 0;

        #10 $finish;

      end

  •   always #5 clk = ~clk;

  • endmodule

Observations