Instructions
  • The verilog module and testbench code are partially filled and divided into code blocks.
  • Drag and drop these code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks
  • Once you have completed the code and rearranged the blocks as required, click on validate. This will give the output truth table as per the code and will also give a success/failure message accordingly.
  • Clicking on reset will reset the experiment and you can start your practice again.
Verilog Module
  • // Define module name, inputs and outputs

    module (

       ,

      input    ,

      input    ,

      output

    );

  •  // Define the functionality of this module.

      assign      ( )    |    ( )   ;

  • // End of the module
    endmodule
Verilog Testbench
  • // Define Test Bench name

    module ;

  • // Declare the input and output variables

      reg ;

      reg ;

      reg ;

      wire ;

  •   // Instantiate the MUX module

       uut (

         ,

         ,

         ,

         ) ;

  • // Initial Block

      initial begin

        // Defining the input waves A, B

        A = 0; B = 0; S = 0;
        #1
        A = 0; B = 0; S = 1;
        #1
        A = 0; B = 1; S = 0;
        #1
        A = 0; B = 1; S = 1;
        #1
        A = 1; B = 0; S = 0;
        #1
        A = 1; B = 0; S = 1;
        #1
        A = 1; B = 1; S = 0;
        #1
        A = 1; B = 1; S = 1;


        $finish;
      end

  • // End of the module
    endmodule
Observations