Tomasulo Algorithm Simulator

Interactive demonstration of dynamic scheduling and out-of-order execution using the Tomasulo algorithm. Explore register renaming, reservation stations, and instruction-level parallelism.

How to Use This Simulator

Key Concepts:

  • Reservation Stations: Buffer instructions and implement register renaming
  • Common Data Bus: Broadcasts results to all waiting instructions
  • Register Renaming: Eliminates false dependencies (WAR/WAW)
  • Out-of-Order Execution: Instructions complete as soon as operands are ready

Instructions:

  1. Select instruction type (ADD, SUB, MUL, DIV, LOAD, STORE)
  2. Specify destination and source registers
  3. For memory operations, provide address/offset
  4. Click "Issue Instruction" to add to pipeline
  5. Use "Step" or "Run" to execute instructions
  6. Observe reservation stations and register renaming

Instruction Input Panel

System Status

Clock Cycle: 0
Instructions Issued: 0
Instructions Completed: 0
IPC: 0.00

Reservation Stations

Add/Sub Units

Tag Busy Op Vj Vk Qj Qk

Multiply/Divide Units

Tag Busy Op Vj Vk Qj Qk

Load/Store Units

Tag Busy Op Address Value Q

Register Alias Table

Register Value Qi (Reservation Station)

Functional Units Status

Unit Status Instruction Cycles Left

Instruction Timeline

No instructions issued yet. Add instructions to see the execution timeline.

Common Data Bus Activity

No CDB activity yet. Execute instructions to see result broadcasts.

Performance Analysis

Structural Hazards: 0
RAW Dependencies: 0
WAR Eliminated: 0
WAW Eliminated: 0
Resource Utilization:
0%

Add/Sub Units

0%

Mul/Div Units

0%

Load/Store Units