Aim of the experiment

To understand and simulate the Tomasulo algorithm for dynamic scheduling in out-of-order execution processors. This experiment aims to:

1. Demonstrate Dynamic Scheduling: Understand how the Tomasulo algorithm enables out-of-order execution while maintaining program correctness through register renaming and reservation stations.

2. Visualize Instruction Pipeline: Observe how instructions flow through different stages - Issue, Execute, and Write-back - and how hazards are resolved dynamically.

3. Analyze Register Renaming: Study how the algorithm eliminates false dependencies (WAR and WAW hazards) through register renaming using reservation stations.

4. Examine Reservation Stations: Understand the role of reservation stations in buffering instructions, resolving dependencies, and enabling parallel execution.

5. Evaluate Performance Impact: Analyze instruction throughput, pipeline utilization, and the impact of different instruction types on overall performance.

6. Explore Real-world Applications: Gain insights into how modern superscalar processors achieve high performance through dynamic scheduling and out-of-order execution.