module (
,
input ,
output
);
assign ;
module ;
// Declare the input and output variables
reg ;
reg ;
wire ;
uut
(
,
,
) ;
initial begin
// Defining the input waves A, B
A = 0;
B = 0;
#1
A = 0;
B = 1;
#1
A = 1;
B = 0;
#1
A = 1;
B = 1;
$finish;
end