Instructions
  • The Verilog module and testbench code are divided into colored code blocks for clarity.
  • Drag and drop the code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks by entering the required values in the input fields.
  • Click on Validate after arranging and completing the code blocks. If the code is correct, you will see the output table and a success/failure message.
  • Click on Reset to clear the workspace and start over.
Verilog Module
  • // Define module name, inputs and outputs

    module (

       ,

      input ,

      output reg

    );

  •  // Define the functionality of this module.

     always @ ( )

    begin

            ;

    end

  • // End of the module
    endmodule
Verilog Testbench
  • // Define Test Bench name

    module ;

  • // Declare the input and output variables

      reg ;

      reg ;

      wire ;

  •   // Instantiate the D Flip Flop module

       DFF (

         ,

         ,

         ) ;

  • // Initial Block

      initial begin

        CLK = 0;

        // Defining the input D Wave
        // 

        D = 0;
        #5 D = _ ;
        #5 D = _ ;
        #5 D = _ ;
        #5 D = _ ;


        $finish;
      end

  • // Define the CLK (Clock) Wave

      always begin

        #2 CLK = ~CLK;

      end

  • // End of the module
    endmodule
Observations