Instructions
  • The D Flip Flop module and testbench code are partially filled and divided into code blocks.
  • Drag and drop these code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks
  • Once you have completed the code and rearranged the blocks as required, click on validate. This will give the output table as per the code and will also give a success/failure message accordingly.
  • Clicking on reset will reset the experiment and you can start your practice again.
Verilog Module
  • // Define module name, inputs and outputs

    module (

       ,

      input ,

      output reg

    );

  •  // Define the functionality of this module.

     always @ ( )

    begin

            ;

    end

  • // End of the module
    endmodule
Verilog Testbench
  • // Define Test Bench name

    module ;

  • // Declare the input and output variables

      reg ;

      reg ;

      wire ;

  •   // Instantiate the D Flip Flop module

       DFF (

         ,

         ,

         ) ;

  • // Initial Block

      initial begin

        CLK = 0;

        // Defining the input D Wave
        // 

        D = 0;
        #5 D = _ ;
        #5 D = _ ;
        #5 D = _ ;
        #5 D = _ ;


        $finish;
      end

  • // Define the CLK (Clock) Wave

      always begin

        #2 CLK = ~CLK;

      end

  • // End of the module
    endmodule
Observations