Instructions
  • This activity helps you build a SPICE code for a D-Flip-Flop step by step.
  • Each colored code block below is a part of the final code. Fill in the blanks in each block.
  • Arrange the blocks in the correct order (see steps below).
  • Click Validate to check your code. If correct, you will see a report and graphs.
  • Click Reset to start over. Click View PTM_45nm.txt to see the MOSFET model file.
Steps to Build Your Code:
  1. Model File: Add the MOSFET model file and set parameters.
  2. Voltage Source: Define the voltage source for your circuit.
  3. Subcircuits: Describe the inverter, pass transistor, 2:1 mux, D-Latch subcircuits and their connections.
  4. D-Flip-Flop Subcircuit: Define the D-Flip-Flop subcircuit using two D-Latches (master-slave configuration).
  5. Instantiate Subcircuit: Use the D-Flip-Flop subcircuit in your main code.
  6. Input Waveform: Set up the input signals for simulation.
  7. Control Statements: Add commands to run and plot the simulation.
  8. End: Finish your SPICE code.
Spice Code
  • * D_FLip-Flop *

    .include


    * Parameter Declarations

    .PARAM supply=1.2
    .PARAM Lmin=45nm
    .PARAM Wmin=45nm
    .PARAM Wp={2*Wmin}
    .global vdd gnd

  • * Netlist statement to define voltage source

     

  • * Defining the inverter subcircuit
    .subckt inverter in out
    MP1 out in vdd vdd pmos w={Wmin} L={Lmin}
    Mn1 out in 0 0 NMOS W={Wmin} L={Lmin}
    .ends inverter

    * Defining the pass transistor subcircuit
    .subckt pass_transistor control in out
    Xinv control not inverter
    MP1 out not in vdd pmos w={Wp} L={Lmin}
    MN1 out control in 0 nmos W={Wmin} L={Lmin}
    .ends

    * Defining the 2:1 MUX subcircuit
    .subckt mux a b s out
    Xinvs s s_ inverter
    Xpt1 s_ a out pass_transistor
    Xpt2 s b out pass_transistor
    .ends

    * Defining the D-Latch subcircuit
    .subckt d_latch in clk out
    Xinv1 out neg inverter
    Xmux neg in clk temp mux
    Xinv2 temp out inverter
    .ends

  • * Define sub-circuit

    .subckt       
          inverter
            d_latch
            d_latch
    .ends

  • *netlist statement to call the gate sub circuit *gate inputs are 'a', 'clk' and the gate output is 'out'

           

  • *Declaring Input Waveform
    .PARAM trfin=10p
    .PARAM t1 = 10n
    .PARAM t2 = 20n
    .PARAM t3 = 30n
    .PARAM t4 = 40n
    .PARAM t5 = 10n
    .PARAM t6 = 20n
    .PARAM t7 = 30n
    .PARAM half = 5n
    .PARAM quarter = 2.5n

    *Transient Analysis
    .tran 6p 70n

    *Use below line for input (declaring input pwl Waveform)
    *'V1', 'V2' are the PWL source names, 'a', 'clk' are the input names
    V1 a 0 PWL (0 0 'half' 0 'half+trfin' 'supply' 't1' 'supply' 't1+half' 'supply' 't1+half+trfin' 0 't2' 0 't2+half' 0 't2+half+trfin' 'supply' 't3' 'supply' 't3+half' 'supply' 't3+half+trfin' 0 't4' 0 't5' 0 't5+quarter' 0 't5+quarter+trfin' 'supply' 't5+(3*quarter)' 'supply' 't5+(3*quarter)+trfin' 0 't6' 0 't7' 0 )
    V2 clk 0 PWL (0 0 't1' 0 't1+trfin' 'supply' 't2' 'supply' 't2+trfin' 0 't3' 0 't3+trfin' 'supply' 't4' 'supply' 't4+trfin' 0 't5' 0 't5+trfin' 'supply' 't6' 'supply' 't6+trfin' 0 't7' 0)
  • *Control Statements
    .control
    run

    *plots inputs
    plot v(a) v(clk)

    *plots output
    plot v(out)

    .endc
  • *End of the code
    .end
Observations