Instructions
  • Please read the PROCEDURE section carefully before starting the simulation for the experiment.
  • The module and testbench code are partially filled and divided into code blocks.
  • Drag and drop these code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks.
  • Once you have completed the code and rearranged the blocks as required, click on validate. This will give the output table as per the code and will also give a success/failure message accordingly.
  • Clicking on reset will reset the experiment and you can start your practice again.
Verilog Module

  • module (

       ,

      output reg [1:0]

    );

      reg [1:0] counter_up = 2'b00;

  •  always @ ( )

    begin

                  

    end

    assign =

  • // End of the module
    endmodule
Verilog Testbench

  • module ;

  •   reg ;

      wire [1:0] ;

  •    dut (

         ,

         )

  •   initial begin

        CLK = 0;


        $finish;
      end

  •   always begin

        #1 CLK = ~CLK;

      end

  • // End of the module
    endmodule
Observations