Instructions
  • Please read the PROCEDURE section carefully before starting the simulation for the experiment.
  • The verilog module and testbench code are partially filled and divided into code blocks.
  • Drag and drop these code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks.
  • Once you have completed the code and rearranged the blocks as required, click on validate. This will give the output truth table as per the code and will also give a success/failure message accordingly.
  • Clicking on reset will reset the experiment and you can start your practice again.
Verilog Module

  • module (

       ,

      input [1:0]    ,

      output reg

      output reg

      output reg

    );

  •   always@(*) begin

             ;
             ;
             ;

       if(A > B)
               ;
       else if(A < B)
               ;
       else
               ;
      end


  • endmodule
Verilog Testbench

`timescale 1ns/1ns

  • module ;

  •   reg [1:0] ;

      reg [1:0] ;

      wire ;

      wire ;

      wire ;

  •   

       uut (

         ,

         ,

         ,

         ,

         ) ;

  •   initial begin

        A = 2'b00; B = 2'b00;
        #1;
        A = 2'b00; B = 2'b01;
        #1;
        A = 2'b00; B = 2'b10;
        #1;
        A = 2'b00; B = 2'b11;
        #1;
        A = 2'b01; B = 2'b00;
        #1;
        A = 2'b01; B = 2'b01;
        #1;
        A = 2'b01; B = 2'b10;
        #1;
        A = 2'b01; B = 2'b11;
        #1;
        A = 2'b10; B = 2'b00;
        #1;
        A = 2'b10; B = 2'b01;
        #1;
        A = 2'b10; B = 2'b10;
        #1;
        A = 2'b10; B = 2'b11;
        #1;
        A = 2'b11; B = 2'b00;
        #1;
        A = 2'b11; B = 2'b01;
        #1;
        A = 2'b11; B = 2'b10;
        #1;
        A = 2'b11; B = 2'b11;


        $finish;
      end


  • endmodule
Observations