MSI Cache Coherence Protocol Simulator

Interactive demonstration of the MSI (Modified-Shared-Invalid) cache coherence protocol for multiprocessor systems. Observe how cache states transition and maintain data consistency.

How to Use This Simulator

MSI Protocol States:

  • M (Modified): Cache line is modified, exclusive to this processor
  • S (Shared): Cache line is shared, read-only, consistent with memory
  • I (Invalid): Cache line is invalid, not present in this cache

Instructions:

  1. Select a processor (P0 or P1)
  2. Choose an operation (Read or Write)
  3. Select a memory address (0x0 to 0x3)
  4. For writes, enter a data value
  5. Click "Execute Operation" to see the protocol in action

Simulation Controls

Cache State Diagrams

Processor 0 Cache State
Processor 1 Cache State

Processor Cache States

Processor 0 Cache

Cache Index State Data Valid
Cache Performance: Hits: 0, Misses: 0

Processor 1 Cache

Cache Index State Data Valid
Cache Performance: Hits: 0, Misses: 0

Bus Transaction Log & State Transitions

No operations performed yet. Execute an operation to see the transaction log.