Instructions
  • Please read the PROCEDURE section carefully before starting the simulation for the experiment.
  • The verilog module and testbench code are partially filled and divided into code blocks.
  • Drag and drop these code blocks to arrange them in the correct order for the code to work.
  • Complete the partially filled code blocks
  • Once you have completed the code and rearranged the blocks as required, click on validate. This will give the output truth table as per the code and will also give a success/failure message accordingly.
  • Clicking on reset will reset the experiment and you can start your practice again.
Verilog Module

  • module (

       ,

      input  ,

      output

      output

    );

  •   assign        ;

      assign        ;


  • endmodule
Verilog Testbench

`timescale 1ns/1ns

  • module ;

  •   reg ;

      reg ;

      wire ;

      wire ;

  •   

       uut (

         ,

         ,

         ,

         ) ;

  •   initial begin

        A = 0;
        B = 0;
        #1
        A = 0;
        B = 1;
        #1
        A = 1;
        B = 0;
        #1
        A = 1;
        B = 1;

    for full adder

        a = 0; b = 0; cin = 0;
        #1
        a = 0; b = 0; cin = 1;
        #1
        a = 0; b = 1; cin = 0;
        #1
        a = 0; b = 1; cin = 1;
        #1
        a = 1; b = 0; cin = 0;
        #1
        a = 1; b = 0; cin = 1;
        #1
        a = 1; b = 1; cin = 0;
        #1
        a = 1; b = 1; cin = 1;


        $finish;
      end


  • endmodule
Observations